UltraTechnology Design Requirements

Parameter	UltraBridge/UltraInductor Requirement
Base Conductor	WTi/Au
Base Conductor Thickness Å	5,000 to 10,000
Minimum Line (Base) mil (µm)	0.4 (10)
Minimum Gap (Base) mil (µm)	0.4 (10)
Dielectric	Si₃N₄
Dielectric Constant	6.0
Dielectric Thickness Å	~20,000
Capacitance Density pF/mil2	N/A
Dielectric Overlap of Base Conductor mil (µm)	1.0 (25) min.
Dielectric Vias mil (µm)	1.0 (25) min.
Dielectric Pads mil (µm)	3.0 (75) min.
Top Conductor	To design
Top Conductor Thickness	2x dielectric thickness
Capacitor Value Range pF	N/A
Capacitor Tolerance %	N/A
Capacitor Around Via	N/A
Minimum Line (Top Conductor) mil (µm)	1.0 (25)
Minimum Gap (Top Conductor) mil (µm)	0.5 (12)
Material	99.6% Al₂O₃ & AlN*
Substrate Surface Finish	Polished
* Subject to Engineering Review mil = 0.001″ = .025mm = 25.4µm

Parameter	UltraCapacitor Requirement
Base Conductor	WTi/Au
Base Conductor Thickness Å	0.5x dielectric thickness
Minimum Line (Base) mil (µm)	N/A
Minimum Gap (Base) mil (µm)	N/A
Dielectric	Si3N4
Dielectric Constant	6.0
Dielectric Thickness Å	~5,000 to ~10,000
Capacitance Density pF/mil2	0.035 to 0.07
Dielectric Overlap of Base Conductor mil (µm)	1.0 (25) min.
Dielectric Vias mil (µm)	N/A
Dielectric Pads mil (µm)	N/A
Top Conductor	To design
Top Conductor Thickness	2x dielectric thickness
Capacitor Value Range pF	2.250
Capacitor Tolerance %	±10 (50 pf)
Capacitor Around Via	Acceptable*
Minimum Line (Top Conductor) mil (µm)	N/A
Minimum Gap (Top Conductor) mil (µm)	N/A
Material	99.6% Al₂O₃ / AlN*
Substrate Surface Finish	Polished
* Subject to Engineering Review mil = 0.001″ = .025mm = 25.4µm